ispgds22/14 in-system programmable generic digital switch tm features high-speed switch matrix 7.5 ns maximum propagation delay ? ypical icc = 25 ma ultramos advanced cmos technology flexible i/o macrocell any i/o pin can be input, output, or fixed ttl high or low programmable output polarity multiple outputs can be driven by one input in-system programmable (5-volt only) programming time of less than one second 4-wire programming interface minimum 10,000 program/erase cycles ? 2 cell technology non-volatile reprogrammable cells 100% tested/100% yields high speed electrical erasure (<100ms) 20 year data retention applications include: software-driven hardware configuration multiple dip switch replacement software configuration of add-in boards configurable addressing of i/o boards multiple clock source selection cross-matrix switch electronic signature for identification the lattice semiconductor ispgds family is an ideal solution for reconfiguring system signal routing or replacing dip switches used for feature selection. with today s demands for customer ease of use, there is a need for hardware which is easily reconfigured electronically without dismantling the system. the ispgds devices address this challenge by replacing conventional switches with a software configurable solution. since each i/o pin can be set to an independent logic level, the ispgds devices can replace most dip switch functions with about half the pin count, and without the need for additional pull-up resistors. in addition to dip switch replacement, the ispgds devices are useful as signal routing cross-matrix switches. this is the only non-volatile device on the market which can provide this flexibility. with a maximum tpd of 7.5ns, and a typical active icc of only 25 ma, these devices provide maximum performance at very low power levels. the ispgds devices may be programmed in-sys- tem, using 5 volt only signals, through a simple 4-wire program- ming interface. the ispgds devices are manufactured using lattice semiconductor s advanced non-volatile e 2 cmos process which combines cmos with electrically erasable (e 2 ) floating gate technology. high speed erase times ( < 100ms) allow the devices to be reprogrammed quickly and efficiently. each i/o macrocell can be configured as an input, an inverting or non-inverting output, or a fixed ttl high or low output. any i/o pin can be driven by any other i/o pin in the opposite bank. a single input can drive one or more outputs in the opposite bank, allowing a signal (such as a clock) to be distributed to multiple des- tinations on the board, under software control. the i/os accept and drive ttl voltage levels. unique test circuitry and reprogrammable cells allow complete ac, dc, and functional testing during manufacture. as a result, lattice semiconductor is able to deliver 100% field programma- bility and functionality of all lattice semiconductor products. in addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified. programmable switch matrix bank b bank a i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 vcc c0 c1 c2 switch matrix 0 1 1 0 1 1 0 0 4:1 mux closed only when c0=1 and c1=0 i/o cell copyright ?2003 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. november 2003 t el. (503) 268-8000; 1-800-lattice; fax (503) 268--8037; http://www.latticesemi.com ispgds_03 functional block diagram (ispgds22) description discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications ispgds 2 part number description ezisxirta ms nipo/ i) sn(dp t) am(bs i) am(cc i# gniredr oe gakcap 11x1 12 25 . 75 20 4j 7-22sdgps ic clpdael-82 7x 74 15 . 75 20 4j 7-41sdgps ic clpdael-02 blank = commercial grade package speed (ns) xxxxxxxx xx x x device name _ j = plcc ispgds22 ispgds14 ispgds ordering information commercial grade specifications discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications ispgds 3 2 20 a0a1a2 vcc a4 mode a3 sdi b0 sclk gnd b3 sdo b2 b1 b6a6a5 b5 b4 4 6 8 10 12 14 16 18 ispgds14 ispgds22 28-pin plcc 20-pin plcc mode a3 a4 vcc a5 a6 a7 2 a8 a9 a10 b10 b9 b8 sdo sdi a2 a1 a0 b0 b1 b2 b3 b4 b5 gnd b6 b7 sclk 28 426 5 7 9 11 12 14 16 18 19 21 23 25 pin configuration discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications ispgds 4 the ispgds family of devices uses a standard jedec file, as used for programmable logic devices, to describe device pro- gramming information. popular logic compilers, such as abel and cupl, can produce the jedec files for these devices. the jedec files can be used to program the ispgds devices in a number of ways, which are shown in the section titled isp architecture and programming. electronic signature an electronic signature word is provided with every ispgds device. it contains 32 bits of reprogrammable memory that can contain user defined data. some uses include user id codes, revision numbers, or inventory control. note: the electronic signature is included in checksum calculations. changing the electronic signature will alter the fuse checksum in the jedec fusemap. ispgds family overview there are three members of the ispgds family, the ispgds22 and ispgsd14. the numerical portion of the part name indi- cates the number of i/o cells available. all of the devices are available in a plcc package. each of the devices operate identically, with the only difference being the number of i/o cells available. the ispgds devices are all programmed through a four-pin interface, using ttl level signals. the four dedicated program- ming pins are named mode, sdi, sdo, and sclk. no high- voltage is needed, as the voltages needed for programming are generated internally. programming of the entire device, includ- ing erasure, can be done in less than one second. during the programming operation, all i/o pins will be tri-stated. further details of the programming process can be found in the in- system programming section later in this datasheet. the i/o cells in each device are divided equally into two banks (bank a and bank b). each i/o cell can be configured as an input, an inverting output, a non-inverting output, or set to a fixed ttl high or low. a switch matrix connects the i/o banks, allowing an i/o cell in one bank to be connected to any of the i/ o cells in the other bank. a single i/o cell configured as an input can drive one or more i/o cells in the other bank. the full i/o macrocell, which is identical for each of the i/o pins, is shown below. the allowable configurations are shown on the following page. in-system programmability the ispgds family of devices feature in-system programmable technology. by integrating all the high voltage programming circuitry on-chip, programming can be accomplished by simply shifting data into the device. once the function is programmed, the non-volatile e 2 cmos cells will not lose the pattern even when the power is turned off. all necessary programming is done via four ttl level logic interface signals. these four signals are fed into the on-chip programming circuitry where a state machine controls the programming. the interface signals are serial data in (sdi), serial data out (sdo), serial clock (sclk) and mode (mode) control. for details on the operation of the internal state machine and programming of ispgds devices please refer to the isp architecture and programming section in this data book. device programming discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications ispgds 5 vcc c0 c1 c2 switch matrix 0 1 1 0 1 1 0 0 4:1 mux closed only when c0=1 and c1=0 configuration for active high output - c0 = 0. - c1 = 1. - c2 = 1. configuration for dedicated input - c0 = 1. - c1 = 0. - c2 = 1. configuration for active low output - c0 = 0. - c1 = 0. - c2 = 1. configuration for fixed ttl high output - c0 = 0. - c1 = 1. - c2 = 0. configuration for fixed ttl low output - c0 = 0. - c1 = 0. - c2 = 0. note 1: the development software configures all of the architecture control bits and checks for proper pin usage automatically. note 2: the default configuration for unused pins is for all configuration bits set to one, which produces a tri-stated output. i/o macrocell i/o macrocell configurations from switch matrix from switch matrix vcc to switch matrix discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications ispgds 6 capacitance (t a = 25 c, f = 1.0 mhz) recommended operating cond. commercial devices: ambient temperature (t a ) ............................... 0 to 75 c supply voltage (v cc ) with respect to ground ..................... +4.75 to +5.25v absolute maximum ratings (1) supply voltage v cc ........................................ ?5 to +7v input voltage applied .......................... ?.5 to v cc +1.0v off-state output voltage applied ......... ?.5 to v cc +1.0v storage temperature ................................ ?5 to 150 c ambient temperature with power applied ........................................... ?5 to 125 c 1. stresses above those listed under the ?bsolute maximum ratings?may cause permanent damage to the device. these are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). dc electrical characteristics over recommended operating conditions (unless otherwise specified) symbol parameter condition min. typ. 2 max. units v il input low voltage vss ?0.5 0.8 v v ih input high voltage 2.0 vcc+1 v i il input or i/o low leakage current 0v v in v il (max.) ?0 a i ih input or i/o high leakage current 3.5v v in v cc 10 a v ol output low voltage i ol = max. vin = v il or v ih 0.5 v v oh output high voltage i oh = max. v in = v il or v ih 2.4 v i ol low level output current 8 ma i oh high level output current ?.2 ma i os 1 output short circuit current v cc = 5v v out = 0.5v t a = 25 c ?0 ?30 ma commercial 1) one output at a time for a maximum duration of one second. vout = 0.5v was selected to avoid test problems caused by tester ground degradation. characterized but not 100% tested. 2) typical values are at vcc = 5v and t a = 25 c symbol parameter maximum* units test conditions c i/o i/o capacitance (as input or output) 8 pf v cc = 5.0v, v i = 2.0v *characterized but not 100% tested. i sb standby power inputs = 0v outputs open l-7 15 25 ma supply current i cc operating power v il = 0.5v v ih = 3.0v l -7 25 40 ma supply current f toggle = 15mhz outputs open discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications ispgds 7 switching waveforms ac switching characteristics over recommended operating conditions input pulse levels gnd to 3.0v input rise and fall times 2ns 10% ?90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure 3-state levels are measured 0.5v from steady-state active level. output load conditions (see figure) t est condition r 1 r 2 c l a 470 ? 390 ? 50pf t pd a input to output delay one input driving one output 1 7.5 ns f max a maximum input frequency one output switching 50 mhz t wh a input pulse duration, high 10 ns t wl a input pulse duration, low 10 ns min. max. p arameter units test cond. description input to output delay input pulse width/ fmax valid input input t pd output t wh t wl 1/ f max input test point c * l from output (o/q) under test +5v *c l includes test fixture and probe capacitance r 2 r 1 com switching test conditions discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications ispgds 8 typical ac and dc characteristic diagrams normalized tpd vs vcc supply voltage (v) normalized tpd 0.8 0.9 1 1.1 1.2 1.3 4.50 4.75 5.00 5.25 5.50 pt h->l pt l->h normalized tpd vs temp temperature (deg. c) normalized tpd 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 pt h->l pt l->h delta tpd vs # of outputs switching number of outputs switching delta tpd (ns) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 1234567891011 rise fall delta tpd vs output loading output loading (pf) delta tpd (ns) -4 -2 0 2 4 6 8 10 12 14 050 100 150 200 250 300 rise fall input clamp (vik) vik (v) iik (ma) 0 10 20 30 40 50 60 70 80 90 -2.00 -1.50 -1.00 -0.50 0.00 delta icc vs vin (1 input) vin (v) delta icc (ma) 0 1 2 3 4 5 6 7 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 normalized icc vs freq. frequency (mhz) normalized icc 0.90 1.00 1.10 1.20 1.30 0255075 100 voh vs ioh ioh(ma) voh (v) 3 3.25 3.5 3.75 4 4.25 0.00 1.00 2.00 3.00 4.00 vol vs iol iol (ma) vol (v) 0 0.5 1 1.5 2 2.5 3 0.00 20.00 40.00 60.00 80.00 normalized icc vs vcc supply voltage (v) normalized icc 0.80 0.90 1.00 1.10 1.20 4.50 4.75 5.00 5.25 5.50 voh vs ioh ioh(ma) voh (v) 0 1 2 3 4 5 0.00 10.00 20.00 30.00 40.00 50.00 60.00 normalized icc vs temp temperature (deg. c) normalized icc 0.8 0.9 1 1.1 1.2 -55 -25 0 25 50 75 100 125 discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
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